Advancements in Ruthenium Nano-TSV for 3D Integrated Circuits
A new integrated process utilizing ruthenium-based nano TSVs and all-dry thinning techniques enhances backside power delivery for 3D ICs. This development addresses routing challenges at nodes beyond 3 nm, promising improved energy efficiency and reliability in advanced semiconductor applications.
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A research team has created an integrated manufacturing process that combines ruthenium-based nano through-silicon vias with all-dry thinning of silicon-on-insulator wafers. This method is designed to support backside power-delivery networks, crucial for advanced three-dimensional integrated circuits, particularly at nodes smaller than 3 nm where copper vias face significant limitations.
The process achieved an aspect ratio of 10.4:1 and critical dimensions down to 39 nm, with a resistivity of 19.9 μΩ·cm. Additionally, the team reported an average line resistance of 29 Ω/μm for the vias and demonstrated reliability through thermal cycling and electromigration tests. This innovative approach may lead to enhanced performance and energy efficiency in future semiconductor devices.
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