Synopsys Launches Software-Defined Hardware-Assisted Verification Platforms for AI Chip Development
Synopsys has introduced new software-defined hardware-assisted verification (HAV) platforms, enhancing performance and scalability for AI chip verification. The ZeBu Server 5 offers up to 2x performance, while the new HAPS-200 12 and ZeBu-200 12 FPGA platforms provide double the capacity for mainstream designs. These advancements facilitate faster detection of subsystem-level bugs and support complex AI architectures across data centers and edge applications. The updates are part of Synopsys' efforts to meet the growing demand for efficient AI silicon innovation.
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Synopsys announced advancements in its hardware-assisted verification (HAV) portfolio, including software-defined platforms designed to enhance AI chip verification. The ZeBu Server 5 achieves up to 2x performance improvement, while the new HAPS-200 12 and ZeBu-200 12 FPGA platforms offer 2x capacity for various AI applications.
These platforms address the increasing complexity of AI chip designs by enabling faster detection of bugs within subsystems. The launch is part of a broader initiative to support AI silicon innovation from data center to edge, aligning with rising market demands. The new capabilities are available immediately, with ongoing enhancements planned.
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