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Synopsys Launches Software-Defined Hardware-Assisted Verification Platforms for AI Chip Development

DATA AND AI INFRASTRUCTURE

Synopsys announced advancements in its hardware-assisted verification (HAV) portfolio, including software-defined platforms designed to enhance AI chip verification. The ZeBu Server 5 achieves up to 2x performance improvement, while the new HAPS-200 12 and ZeBu-200 12 FPGA platforms offer 2x capacity for various AI applications.

These platforms address the increasing complexity of AI chip designs by enabling faster detection of bugs within subsystems. The launch is part of a broader initiative to support AI silicon innovation from data center to edge, aligning with rising market demands. The new capabilities are available immediately, with ongoing enhancements planned.

Synopsys Launches Software-Defined Hardware-Assisted Verification Platforms for AI Chip Development
Mar 13, 2026, 6:00 AM

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