TIER IV Collaborates with JST on Open-Source AI Chip Design for Autonomous Driving
TIER IV has joined JST's Next-Generation Edge AI Semiconductor R&D Program to develop a software-defined SoC for Level 4 autonomous driving. This partnership aims to create open-source AI chip designs, enhancing power efficiency and adaptability in autonomous driving applications.
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TIER IV is collaborating with the Japan Science and Technology Agency (JST) to innovate a software-defined system-on-chip (SoC) aimed at Level 4 autonomous driving. The initiative will produce open-source AI chip designs and related toolchains, supporting the Autoware software ecosystem.
TIER IV will focus on optimizing the performance per watt of its AI chip, which will integrate dedicated compute circuits for operations common in Transformer models, enhancing efficiency in sensor data processing. The Tensor Operator Set Architecture (TOSA) will facilitate flexible adaptations to AI models, allowing software updates to refine performance without redesigning the chip.
This open-source approach could stimulate advancements in semiconductor technology, fostering collaboration among manufacturers and developers. The emphasis on transparency and verifiability may improve safety protocols in autonomous driving applications.
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