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L&T Semiconductor Technologies (LTSCT) in Bengaluru is leading the way in Design for Testability (DFT) engineering for semiconductor chips, including System on Chips (SoCs). The organization employs various DFT techniques such as Memory Built-In Self-Test (MBIST), compressor-based scan chain insertion, and Boundary Scan insertion in compliance with IEEE 1149.1 and 1149.6 standards.

Additional methods include Logic BIST, Analog BIST for blocks like PLLs, ADCs, and DACs, and IO Built-In Self-Test methods. DFT simulations are performed to analyze results for comprehensive test coverage, while debugging and resolving DFT-related issues are crucial throughout the design process.