S2C, MachineWare, and Andes Launch RISC-V Co-Emulation Solution for Chip Development

S2C, MachineWare, and Andes Technology have introduced a co-emulation solution to enhance RISC-V chip design. This solution combines MachineWare's SIM-V virtual platform, S2C's Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes' AX46MPV RISC-V CPU core, facilitating a unified environment for hardware and software co-verification.

It supports a 'shift-left' verification approach, allowing parallel development of hardware and software to decrease project risk and development time. The SIM-V platform offers high-performance simulation with comprehensive support for Andes RISC-V cores, enabling detailed visibility and debugging capabilities.

The AX46MPV CPU is designed for high-performance applications, including data center AI and Linux-capable platforms. The solution targets multiple development stages, including pre-silicon software development and system performance tuning, aiming to accelerate time-to-market and improve software maturity.